Antialiasing in BBD Chips using BLEP
- Authors
- Leonardo Gabrielli1, Stefano D'Angelo2, Stefano Squartini1
- Status
- Published in Proceedings of the 28th International Conference on Digital Audio Effects (DAFx25), pp. 71–77, Ancona, Italy, September 2025
- 1
- Università Politecnica delle Marche, Ancona, Italy
- 2
- Orastron Srl, Agropoli, Italy
BibTeX
@inproceedings{gabrielli2025bbd,
title={Antialiasing in BBD Chips using BLEP},
author={Gabrielli, Leonardo and D'Angelo, Stefano and Squartini, Stefano},
booktitle={Proc. 28\textsuperscript{th} Intl. Conf. Digital Audio Effects (DAFx25)},
pages={71--77},
month={September},
year={2025},
address={Ancona, Italy}
}Abstract
Several methods exist in the literature to accurately simulate Bucket Brigade Device (BBD) chips, which are widely used in analog delay-based audio effects for their characteristic lo-fi sound, which is affected by noise, nonlinearities and aliasing. The latter is a desired quality, being typical of those chips. However, when simulating BBDs in a discrete-time domain environment, additional aliasing components occur that need to be suppressed. In this work, we propose a novel method that applies the Bandlimited Step (BLEP) technique, effectively minimizing aliasing artifacts introduced by the simulation. The paper provides some insights on the design of a BBD simulation using interpolation at the input for clock rate conversion and, most importantly, shows how BLEP can be effective in reducing unwanted aliasing artifacts. Interpolation is shown to have minor importance in the reduction of spurious components.
Implementation
- N-stages BBD chip model (GNU Octave script)
Sound samples
- Modulated sine w/ center freq 2093 Hz, 4096-stages BBD w/ avg clock rate 10 kHz, sample rate 44.1 kHz, trivial implementation
- Modulated sine w/ center freq 2093 Hz, 4096-stages BBD w/ avg clock rate 10 kHz, sample rate 44.1 kHz, proposed implementation
- Modulated sine w/ center freq 2093 Hz, 4096-stages BBD w/ avg clock rate 50 kHz, sample rate 44.1 kHz, trivial implementation
- Modulated sine w/ center freq 2093 Hz, 4096-stages BBD w/ avg clock rate 50 kHz, sample rate 44.1 kHz, proposed implementation
- Modulated sine w/ center freq 2093 Hz, 4096-stages BBD w/ avg clock rate 90 kHz, sample rate 44.1 kHz, trivial implementation
- Modulated sine w/ center freq 2093 Hz, 4096-stages BBD w/ avg clock rate 90 kHz, sample rate 44.1 kHz, proposed implementation